Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) occupy a dominant position in the current flat panel display market because of the features of small volume, low power consumption and no radiation, etc. For a TFT-LCD, an array substrate and a manufacturing method thereof determine the performance, yield and price of a product. In order to effectively reduce the production cost of the TFT-LCD and improve the yield, the manufacturing process of the array substrate of the TFT-LCD is gradually simplified, and it has been developed from seven mask (7 mask) processes at the beginning to four mask (4 mask) processes on a basis of a slit photolithography technique.
The 4 mask processes adopted for manufacturing an array substrate in the prior art mainly comprise the following steps: Step S11, Gate electrodes and gate lines are formed on a substrate; Step S12, an insulating layer is deposited on the gate electrodes and the gate lines; Step S13, an active layer is deposited on the insulating layer; Step S14, a source/drain electrode layer is deposited on the active layer; Step S15, a PVX protective layer is deposited on the source/drain electrode layer, and via-holes are formed in the protective layer; Step S16, finally, an ITO (Indium Tin Oxide) conductive layer is formed on the protective layer. Since the formations of the gate electrodes, the source/drain electrode layer, the via-holes, and the ITO conductive layer all require mask process, the manufacturing of an array substrate in the prior art needs four mask processes in total. The step S11 utilizing one mask process to form the gate electrodes and the gate lines makes sequent processes complicated, and the performance of the array substrate manufactured is hard to be guaranteed. On the other hand, the insulating layer in the prior art has a thickness of 400 nm, which is relatively thick, and which results in a relatively long charging time of the TFT. The protective layer has a thickness of 250 nm, which is relatively thin, and which results in a relative large capacitance between the data lines and the gate lines and is liable to generate a parasitic capacitance (CgS), causing crosstalk phenomenon to occur between the source/drain electrodes and the gates, and affecting the display quality.